Senior Silicon Design Engineer: AI-Driven PnR & Timing

Xilinx Asia Pacific Pte. Ltd. in Singapore seeks a hands-on physical design engineer to drive RTL/netlist-to-GDS flows across floorplanning, placement, routing and timing closure, using AI-assisted workflows and modern EDA tools to accelerate delivery and improve quality. You will collaborate with RTL, circuit, integration and CAD teams, own or contribute to block- or subsystem-level design, and create reusable automation in Tcl, Python or shell while validating all AI outputs. J-18808-Ljbffr