Design Verification Engineer

Job Description: We are seeking Design Verification Engineer with exposure on Developing and maintaining UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems). What You'll Be Doing: Strong in SV/UVM scale test bench AXI expertise, NOC/Crossbar, Performance Regression/Triage and coverage closure Need asap → Program has already started and is in execution Ability to work on Amazon tools, flows, methodology. Work is in start-up mode with less docume…