Experienced AMS Design Verification Engineer (m/f/d) #200687940 (Ingenieur/in - Elektrotechnik)

SummaryAt Apple, we work daily to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and creative Design Verification Engineer. As a member of our Advanced Technology group, you will have the rare and rewarding opportunity to craft upcoming products, which will delight and encourage millions of Apple’s customers every single day. Do your life’s best work here at Apple! This role is for a Design Verification Engineer who will enable bug-free first silicon for the mixed-signal designs in our NEW London team. The responsibilities include all phases of pre-silicon verification, including but not limited to: construction of verification environments, coding of test scenarios and assertions, and close collaboration with Analog and Digital Design engineers.DescriptionDefinition and design of Self-checking verification environments for multi-layer systems using the SystemVerilog UVM library. The responsibility spans from concept discussions, verification strategy definition and execution of the verification tasks to ensure bug-free tape-outs. The AMS DV engineer goes beyond standard verification techniques and include: - performance-based analysis - power related analysis and scenario design for early power estimation - deliveries of tests for design and test engineering teams - gate-level verification (power and timing) - lab bring-up support A significant part of the AMS DV team focuses on research and innovations to improve verification techniques and tools for mixed-signal systems in order to increase efficiency and quality. Looking forward and establishing cutting edge concepts and methods to support them are part of the AMS DV team’s DNA.ResponsibilitiesMinimum Qualifications- Knowledge of System Verilog test-bench language and UVM (Universal Verification Methodology)- Hands-on experience with constrained random verification environments-