Design Verification Engineer – GLS & Hardware Emulation

Hireroo Ltd in Barcelona seeks a Design Verification Engineer to drive gate-level simulation, hardware emulation and timing verification for advanced ASIC/SoC designs. You will collaborate with RTL, DFT, physical design and firmware teams to validate synthesized designs before silicon. Mid to senior level, you will optimize simulation performance, automate workflows, debug RTL/netlist mismatches, and support emulation bring-up on hardware platforms while contributing to power, timing and J-1880…