Lead High-Speed Verification Engineer – PCIe/UCIe

Hireroo Ltd is seeking a Lead Design Verification Engineer in Barcelona to lead functional verification of high-speed interface protocol blocks at IP and subsystem levels. The role blends hands-on verification with technical leadership across RTL, architecture, firmware and verification teams. You will architect and maintain UVM environments, own verification of PCIe/UCIe/SerDes, and act as protocol expert for AXI, CXS, AHB, CHI. J-18808-Ljbffr