Application Specific Integrated Circuit Verification Engineer

Job Description ASIC UVM Verification Engineer \n Role: Senior ASIC Verification Engineer Industry: Satellite Communications / Semiconductor Experience: 8 years Key requirement: Strong hands-on SystemVerilog and UVM verification experience. \n What the client is looking for \n \n Multiple openings — candidates will be placed where their skills fit best. \n Three verification levels: IP/Block-level, Subsystem-level, and SoC-level. \n Well-rounded UVM engineers who can develop testbenches, debug …