Lead Design Verification for Vision Accelerators

Meta is hiring a Design Verification (DV) lead for accelerators to own verification for complex computer vision and imaging IPs and subsystems. You will define DV strategy across IPs, build scalable DV infrastructure, and drive sign-off across multiple blocks. We seek a senior engineer with extensive SystemVerilog/UVM/C/C++ experience, DV leadership, and a track record of tape-outs. Join a fast-moving silicon team delivering advanced AR/VR hardware. J-18808-Ljbffr