Senior Layout Engineer for Analog & SoC Integration

Curious Tek PTE. LTD. in Singapore is seeking an experienced layout engineer to design digital and analog IC layouts, and to support SoC integration with the front-end team. The role requires hands-on expertise in CMOS layouts and strong problem-solving skills to fix DRC/LVS issues. The ideal candidate holds a bachelor’s degree in Electrical & Electronic Engineering and has 5 years of layout experience, with proficiency in Cadence, Synopsys, and Mentor Calibre. J-18808-Ljbffr