Physcial Design Engineer

The Senior ASIC Physical Design Engineer leads implementation of assigned SoC partitions, focusing on synthesis, place and route, and static timing closure. Working on-site with design, DFT, and architecture teams, this role resolves implementation and signoff issues, manages EM/IR, PDN, LEC, and physical verification for sub-7nm technologies, and refines PD methodologies and custom TCL-based flows while collaborating with EDA vendors to troubleshoot and improve design flows. Execute synthesis,…