RTL/SerDes Design Engineer - DFT & Timing Closure

CURIOUS TEK PTE. LTD.

Singapore1440 - 2160📅 3/10/2026

Descripción

CURIOUS TEK PTE. LTD. seeks an experienced Senior IC Design Engineer to advance SerDes IP products. You will handle Verilog/VHDL RTL design, logic synthesis, and DFT/ATPG, coordinating with physical and RTL teams to meet timing goals. Ideal candidates have 5 years of digital IC design, tape-out experience, and familiarity with Cadence or Synopsys tools, along with strong communication and teamwork skills. J-18808-Ljbffr

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