Physical Design Engineer

Job Description seeking a principal-level physical verification and power-analysis expert to own full-chip PV and power-integrity signoff \n for complex ASIC/SoC designs. The engineer will lead DRC, LVS, ERC, reliability, IR-drop, electromigration, and power \n closure through tapeout using Siemens Calibre and Cadence Voltus. \n KEY RESPONSIBILITIES \n • Own top-level physical verification closure from full-chip integration through final tapeout. \n • Run, debug, and close DRC, LVS, ERC, antenn…