Senior ASIC Physical Design Engineer

As a Senior ASIC Physical Design Engineer, you will execute synthesis, place-and-route, and static timing analysis for SoC partitions, working closely with RTL, architecture, and DFT teams. You will resolve timing, EM/IR, and physical verification issues, drive block-level signoff, refine implementation methodologies, and troubleshoot EDA flows in advanced sub-7nm technologies in an on-site environment. Execute synthesis, place-and-route (PnR), and static timing analysis for assigned ASIC parti…