Senior Physical Verification Engineer: End-to-End Tape-out

dadaconsultants pte. ltd. seeks a Senior/Staff Physical Verification Engineer to own PV signoff for advanced-node ASIC/SoC at the block and full-chip levels. You will collaborate with Place & Route to resolve layout issues and drive tape-out milestones in a fast-paced, high-impact environment. You will harness Calibre and scripting (Python, Perl, Tcl, Make) to automate flows and improve efficiency, contributing to method development and back-end signoff processes. J-18808-Ljbffr