Physical Design Engineer with Cadence Innovus

Conduct EM/IR analysis. Strong experience with Cadence Innovus. Expertise in the complete Physical Design cycle from RTL to Tape-out. Strong TCL and/or PERL scripting skills. Develop and optimize Clock Tree Synthesis (CTS), including custom clock trees, insertion delay reduction, and skew balancing. Perform timing closure using various methodologies and strategies, including top-level STA. Collaborate closely with IC Design and RTL Engineering teams.