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FPGA Design Engineer — AI-Powered Space Payloads

Aistech Space

Barcelona, Cataluña60000 - 100000📅 23/10/2026

Descripción

Aistech Space in Barcelona seeks an expert FPGA Design Engineer to lead next‑gen image acquisition payloads. You’ll architect the digital brain, transforming raw high‑speed sensor data into actionable insights using VHDL and hardware acceleration. You will manage data flow from FPGA pins to AI engines, integrate DMA streams, and ensure timing closure. Join a cross‑functional, agile team and contribute to documentation and blogs. J-18808-Ljbffr
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