Senior Physical ASIC Design Implementation Engineer

Senior Physical ASIC Design Implementation Engineer Physical Implementation engineer for full backend (P&R) projects from netlist-in to GDSII-out flow, for toplevel chips as well as blocklevel blocks in technologies ranging from N3 to 180nm. This with the full understanding of the complete Cadence Innovus Place&Route flow. Additionally, you will take up the role of technical lead in large projects, leading the rest of the backend team involved and to be the connection with the customer. What yo…