Memory Layout Engineer

Memory Layout Engineer Experience: 4–8 years Location – Bangalore Qualifications: Bachelor's or Master's degree in Electrical Engineering, Technology Nodes: TSMC/Samsung – 2nm, 3nm, 5nm, 7nm, and GF nodes Key Skills & Responsibilities: Hands-on experience in layout of memory blocks like control logic, sense amplifiers, I/O blocks, bit cell array, decoders, etc. Strong experience in SRAM/DRAM, memory compiler IPs, and memory periphery circuits Expertise in top-level memory integration, DRC, LVS,…