Senior Staff Engineer Chip Verification

We are seeking an experienced Chip Verification Engineer to execute end-to-end verification of complex System-on-Chip designs, with a focus on Network-on-Chip (NoC), interconnect and system-level verification. The role involves developing verification plans, building and integrating SystemVerilog/UVM testbenches and VIPs, creating C/C++ and Perspec test cases, and performing simulation and debugging across RTL, unit-delay and gate-level environments. Your role Key responsibilities in your new r…