(Sr./Staff) ASIC Design Engineer

Key Responsibilities RTL Design and Verification Develop synthesizable RTL in Verilog/SystemVerilog for custom on-chip test, monitoring, and diagnostic IP targeting analog and mixed-signal failure detection. Design and verify digital logic blocks such as test controllers, sequencing logic, sensor/interface control logic, measurement and monitoring logic, data capture and comparison logic, and failure detection and reporting logic. Build clean register and bus-connected interfaces, for example A…