Advanced Physical Design and Verification Engineer (7036)
TSMC
Alviso, San Jose139843 - 139843📅 8/9/2026
Descripción
Overview of Role As a Advanced Physical Design and Verification Engineer, you will be responsible for the Design Rule Check, Layout vs. Schematic checking and fix all PDV/EMIR/Noise/SigEM violations and errors. You may also do customization and implementation of top clocks and implement timing ECOs on high performance blocks. You will be reporting to Manager of Advanced Chip implementation team at its San Jose Design Center, California and joining a team of engineers dedicated to pushing the en…