Senior Engineer, Physical Design (ASIC/SoC Place & Route) (Austin, TX)(5560)

Overview of Role As a Sr. Physical Design Engineer, you will be responsible for the entire APR implementation flow from RTL-to-GDS that includes synthesis, floorplan, place and route, CTS, STA, and signoff. You will be reporting to Manager of Advanced Chip implementation team at its Austin Design Center, Texas and joining a team of engineers dedicated to pushing the envelope for the world’s leading semiconductor company. We are currently operating in a hybrid work schedule with 4 days in office…