Senior Analog/Mixed-Signal IC Layout Architect

Astera Labs in Singapore is seeking a Senior Analog Mixed-Signal IC Layout Engineer to join our ASIC team. You will work on high-performance compute and networking standards in advanced CMOS, focusing on design, verification, and validation of real-world systems. Requirements include BS/MS in EE/CS, RTL languages Verilog/SystemVerilog, UVM, Python/C/C++, and experience with PCIe, DDR, HBM or Serdes. Curiosity and a strong learning mindset are essential. J-18808-Ljbffr