RTL Design and FPGA Engineer

We are seeking an experienced RTL Design and FPGA Engineer for an opportunity in San Jose, CA. Expertise in Verilog-based synthesizable RTL development, register map implementation, and modular RTL design. Strong experience with FPGA clocking structures and deterministic reset schemes is required. Required experience includes: ● Proven Verilog expertise in synthesizable RTL, register map implementation, and modular design. ● Strong understanding of FPGA clocking structures and deterministic res…