Senior DFT Engineer - ASIC/SoC Test & Validation

Alphaeus Pte Ltd in Singapore seeks a Design for Test (DFT) engineer to drive DFT implementation, verification and support for semiconductor IP, ASIC and SoC projects from pre‑silicon through post‑silicon debug. You will collaborate with RTL, physical design and client teams to insert scan chains, verify DFT rules, generate ATPG patterns and optimize test coverage, area and timing. Proficiency in Tcl, Verilog/SystemVerilog and EDA tools is essential. J-18808-Ljbffr