Senior Design Verification Engineer

Experience: 5 to 15 years of experience as a RTL Verification engineer. Job Description: System Verilog, UVM Good knowledge in AMBA,AX4,AHB IP/SS/SOC verification experience Test Env, test case development Regression debug, coverage analysis Good knowledge in One of the High speed IF protocol like PCIe6, DDR5, Ethernet or USB3 Experience in Synopsys/Cadance Tools usage Qualifications Strong functional verification skills, including Functional Verification and Debugging for complex digital desig…