Physical Design Engineer

Einfochips

San Jose, Santa Clara County120000 - 140000📅 18/7/2026

Descripción

Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks. Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners. Partner with the design team to proactively identify and address potential physical design challenges, enablin…

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