Packaging Design Engineer, High-Speed SerDes & 2.5D/3DIC

Broadcom Inc. in Singapore seeks an experienced ASIC package design engineer to lead high‑speed SerDes flip‑chip‑BGA work for AI, networking, HPC and 5G applications. You will own impedance matching, signal/power integrity, manufacturability, reliability and thermal aspects in collaboration with a global team. The candidate should have 5 years in flip-chip-BGA package design (or 3 with M.Eng), strong SI/PI knowledge, and Cadence APD experience is preferred; 2.5D/3DIC exposure is advantageous. J…