Descripción
CDI à 100% de suite ou à convenir. Postulation uniquement en ligne - merci de mentionner sous source ORP. At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption. Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale. Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future. Job Title: Analog Design Engineer (Advanced Research and Development Department) Key responsibilities: Develop block level specifications and models for target designs Develop, model, design, and verify performance of custom analog circuits in advanced technology nodes Layout design and development, including floor-planning, guiding layout engineers, and post-layout verification Design verification at different levels (pre- and post-layout, variation-aware) Support and collaborate with the design team, including other design and layout engineers, architects and chip level integration engineers, modeling and system level designers. Support for post-silicon lab bring-up, debug, characterization and productization. Produce reports (progress report, analysis, design, modeling, and verification reports) Participate in developing concept level architectures and circuits Skills: Deep understanding on design and layout techniques for high-speed and high-precision circuits, problem solver, and excellent analytical skills. Experience in developing testbenches and simulation setups to analyze performance of target circuits and systems. Skillful in layout techniques, such