Design Validation Engineer

Design Verification Engineer – Full time Location: San Jose, CA & Austin, TX - onsite Client is looking for 5 -12 years experience More emphasis on the candidate who has worked on these protocols : PCIe, Ethernet, die-to-die / chip-to-chip, HBM, DDR. Please find the JD: Job Summary We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and …