Senior ASIC/SoC RTL Design Engineer – RTL Design Analysis

10 years of experience in ASIC/SoC RTL design or a closely related digital design discipline. Strong hands-on experience with Verilog and SystemVerilog RTL. In-depth understanding of digital logic design, RTL coding, and microarchitecture. Experience analyzing complex RTL codebases and understanding existing design behavior. Strong knowledge of FSMs, datapaths, control logic, registers, and digital interfaces. Experience with RTL simulation, debugging, and waveform analysis. Ability to work ind…