Senior ASIC Physical Design Engineer — RTL to GDS Expert

Broadcom in Singapore seeks an experienced IC Design Engineer to design and implement 100–400 million gate ICs using 7nm/5nm/3nm/2nm nodes. You will drive RTL to GDSII flows, including synthesis, placement, clock tree, routing, and verification, applying GPU/CPU/DSP architectural knowledge. UNIX/Linux scripting is advantageous, with 8 years in the field preferred. Candidates will use Synopsys, Cadence, and Siemens tools in a fast-paced R&D environment, collaborating across teams to meet J-18808…