Senior ASIC Physical Design Engineer: RTL to GDS, 2nm-5nm

Broadcom Singapore Pte Ltd is seeking an experienced Senior IC Design Engineer to drive RTL to GDS flows across 7nm/5nm/3nm/2nm nodes. You will leverage your 8 years in IC/SoC design to deliver robust designs and ensure timing closure with advanced EDA tools. The role requires strong UNIX/Linux scripting and deep knowledge of GPU/CPU/DSP architectures, plus hands-on experience with Synopsys, Cadence, and Siemens toolchains. J-18808-Ljbffr